library IEEE;
use ieee.std_logic_1164.all;

entity logic_unit is
	port
	(
		a, b: in	std_logic_vector (7 downto 0);
		sel : in	std_logic_vector (2 downto 0);
		y	: out	std_logic_vector (7 downto 0)
	);
end logic_unit;

architecture logic_arch of logic_unit is
begin
with sel select
	y	<=	not a		when	"000",
			not b		when	"001",
			a and b		when	"010",
			a or b		when	"011",
			a nand b 	when	"100",
			a nor b		when	"101",
			a xor b		when	"110",
			a xnor b	when	"111";

end logic_arch;